Fixing newly discovered side channel will likely take a major toll on performance.
  • @GlitterInfection@lemmy.worldEnglish
    1•9 months ago

    This requires local access to do and presently an hour or two of uninterrupted processing time on the same cpu as the encryption algorithm.

    So if you’re like me, using an M-chip based device, you don’t currently have to worry about this, and may never have to.

    On the other hand, the thing you have to worry about has not been patched out of nearly any algorithm:

    https://xkcd.com/538/

  • @Spedwell@lemmy.worldEnglish
    1•9 months ago

    Wow, what a dishearteningly predictable attack.

    I have studied computer architecture and hardware security at the graduate level—though I am far from an expert. That said, any student in the classroom could have laid out the theoretical weaknesses in a “data memory-dependent prefetcher”.

    My gut says (based on my own experience having a conversation like this) the engineers knew there was a “information leak” but management did not take it seriously. It’s hard to convince someone without a cryptographic background why you need to {redesign/add a workaround/use a lower performance design} because of “leaks”. If you can’t demonstrate an attack they will assume the issue isn’t exploitable.

    • @TechNerdWizard42@lemmy.worldEnglish
      -1•9 months ago

      The more probable answer is that the NSA asked for the backdoor to be left in. They do all the time, it’s public knowledge at this point. AMD and Intel chips have the requisite backdoors by design, and so does Apple. The Chinese and Russian designed chips using the same architecture models, do not. Hmmmm… They have other backdoors of course.

      It’s all about security theatre for the public but decrypted data for large organizational consumption.

      • @Spedwell@lemmy.worldEnglish
        1•9 months ago

        I don’t believe that explanation is more probable. If the NSA had the power to compell Apple to place a backdoor in their chip, it would probably be a proper backdoor. It wouldn’t be a side channel in the cache that is exploitable only in specific conditions.

        The exploit page mentions that the Intel DMP is robust because it is more selective. So this is likely just a simple design error of making the system a little too trigger-happy.

    • @lightnegative@lemmy.worldEnglish
      -1•9 months ago

      If you can’t demonstrate an attack they will assume the issue isn’t exploitable.

      Absolutely. Theory doesn’t always equal reality. The security guys submitting CVE’s to pad their resumes should absolutely be required to submit a working exploit. If they can’t then they’re just making needless noise

  • @Zink@pawb.socialEnglish
    -1•9 months ago

    A revolution in composition. First titanium (making phones somehow less durable), and now they can’t even keep their own chips secure because of the composition of the chip lol